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M95040 M95020, M95010
4/2/1 Kbit Serial SPI Bus EEPROM With High Speed Clock
PRELIMINARY DATA
s
Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes) Single Supply Voltage: - 4.5V to 5.5V for M950x0 - 2.5V to 5.5V for M950x0-W - 1.8V to 3.6V for M950x0-R
s
8 1
PSDIP8 (BN) 0.25 mm frame
8 1
TSSOP8 (DW) 169 mil width
s s s s s s s s
5 MHz Clock Rate (maximum) Status Register BYTE and PAGE WRITE (up to 16 Bytes) Self-Timed Programming Cycle Adjustable Size Read-Only EEPROM Area Enhanced ESD Protection 1,000,000 Erase/Write Cycles (minimum) 40 Year Data Retention (minimum)
8 1
SO8 (MN) 150 mil width
DESCRIPTION These SPI-compatible electrically erasable programmable memory (EEPROM) devices are organized as 512 x 8 bits, 256 x 8 bits and 128 x 8 bits (M95040, M95020, M95010). They operate down to 2.5 V (for the -W version of each device), and down to 1.8 V (for the -R version of each device).
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
C D Q Serial Clock Serial Data Input Serial Data Output
D C S W M95xxx
Q
S
W HOLD VCC VSS
Chip Select
HOLD
Write Protect Hold Supply Voltage Ground
VSS
AI01789C
August 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M95040, M95020, M95010
Figure 2A. DIP Connections Figure 2B. SO and TSSOP Connections
M95xxx S Q W VSS 1 2 3 4 8 7 6 5
AI01790C
M95xxx VCC HOLD C D S Q W VSS 1 2 3 4 8 7 6 5
AI01791C
VCC HOLD C D
The M95040 and M95020, M95010 are available in Plastic Dual-in-Line, Plastic Small Outline and Thin Shrink Small Outline packages. Each memory device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 3. The device is selected when the chip select input (S) is held low. Communications with the chip can be interrupted using the hold input (HOLD). Write operations are disabled by the write protect input (W).
SIGNAL DESCRIPTION Serial Output (Q) The output pin is used to transfer data serially out of the Memory. Data is shifted out on the falling edge of the serial clock. Serial Input (D) The input pin is used to transfer data serially into the device. Instructions, addresses, and the data to be written, are each received this way. Input is latched on the rising edge of the serial clock. Serial Clock (C) The serial clock provides the timing for the serial interface (as shown in Figure 4). Instructions, addresses, or data are latched, from the input pin,
Table 2. Absolute Maximum Ratings 1
Symbol TA TSTG TLEAD VO VI VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering Output Voltage Range Input Voltage Range Supply Voltage Range Electrostatic Discharge Voltage (Human Body model) Electrostatic Discharge Voltage (Machine model) 3
2
Value -40 to 125 -65 to 150 PSDIP8: 10 sec SO8: 40 sec TSSOP8: t.b.c. 260 215 t.b.c. -0.3 to VCC+0.6 -0.3 to 6.5 -0.3 to 6.5 4000 400
Unit C C C V V V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100 pF, 1500 ) 3. EIAJ IC-121 (Condition C) (200pF, 0W).
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M95040, M95020, M95010
Figure 3. Microcontroller and Memory Devices on the SPI Bus
SPI Interface with SDO (CPOL, CPHA) = SDI ('0', '0') or ('1', '1') SCK Master (ST6, ST7, ST9, ST10, Others)
CQD M95xxx
CQD M95xxx S
CQD M95xxx S
CS3
CS2
CS1
S
AI01958C
on the rising edge of the clock input. The output data on the Q pin changes state after the falling edge of the clock input. Chip Select (S) When S is high, the memory device is deselected, and the Q output pin is held in its high impedance state. Unless an internal write operation is underway, the memory device is placed in its stand-by power mode. After power-on, a high-to-low transition on S is required prior to the start of any operation. Write Protect (W) This pin is for hardware write protection. When W is low, writes to the device are disabled, but all other operations remain enabled. When W is high, write operations are enabled. If W goes low at any time before the last bit, D0, of the data stream, the write enable latch is reset, thus preventing the write from taking effect. No action on W or on the write enable latch can interrupt a write cycle which has commenced, though. Hold (HOLD) The HOLD pin is used to pause the serial communications between the SPI memory and controller, without losing bits that have already been decoded in the serial sequence. For a hold condition to occur, the memory device must already have been selected (S = 0). The hold condition starts when the HOLD pin is held low while the clock pin (C) is also low (as shown in Figure 14).
During the hold condition, the Q output pin is held in its high impedance state, and the levels on the input pins (D and C) are ignored by the memory device. It is possible to deselect the device when it is still in the hold state, thereby resetting whatever transfer had been in progress. The memory remains in the hold state as long as the HOLD pin is low. To restart communication with the device, it is necessary both to remove the hold condition (by taking HOLD high) and to select the memory (by taking S low). The Memory can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: (CPOL, CPHA) = ('0','0') or (CPOL,CPHA) = ('1','1'). For these two modes, input data is latched in by the low to high transition of clock C, and output data is available from the high to low transition of Clock (C). The difference between (CPOL, CPHA) = (0, 0) and (CPOL, CPHA) = (1, 1) is the stand-by polarity: C remains at '0' for (CPOL, CPHA) = (0, 0) and C remains at '1' for (CPOL, CPHA) = (1, 1) when there is no data transfer. OPERATIONS All instructions, addresses and data are shifted serially in and out of the chip. The most significant bit is presented first, with the data input (D) sampled on the first rising edge of the clock (C) after the chip select (S) goes low.
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M95040, M95020, M95010
Figure 4. Data and Clock Timing
CPOL CPHA
0
0
C
1
1
C
D or Q
MSB
LSB
AI01438
Every instruction starts with a single-byte code, as summarized in Table 3. This code is entered via the data input (D), and latched on the rising edge of the clock input (C). To enter an instruction code, the product must have been previously selected (S held low). If an invalid instruction is sent (one not contained in Table 3), the chip automatically deselects itself. Write Enable (WREN) and Write Disable (WRDI) The write enable latch, inside the memory device, must be set prior to each WRITE and WRSR operation. The WREN instruction (write enable) sets this latch, and the WRDI instruction (write disable) resets it.
Table 3. Instruction Set
Instruc tion WREN WRDI RDSR WRSR READ WRITE Description Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Write Data to Memory Array Instruction Format 0000 X110 0000 X100 0000 X101 0000 X001 0000 A8011 0000 A8010
Note: 1. A8 = 1 for the upper page on the M95040, and 0 for the lower page, and is Don't Care for other devices. 2. X = Don't Care.
Table 4. Status Register Format
b7 1 1 1 1 BP1 BP0 WEL b0 WIP
Note: 1. BP1 and BP0 are read and write bits. 2. WEL and WIP are read only bits. 3. b7 to b4 are read only bits.
The latch becomes reset by any of the following events: - Power on - WRDI instruction completion - WRSR instruction completion - WRITE instruction completion - the W pin is held low. As soon as the WREN or WRDI instruction is received, the memory device first executes the instruction, then enters a wait mode until the device is deselected. Read Status Register (RDSR) The RDSR instruction allows the status register to be read, and can be sent at any time, even during a Write operation. Indeed, when a Write is in progress, it is recommended that the value of the Write-In-Progress (WIP) bit be checked. The value in the WIP bit (whose position in the status register is shown in Table 4) can be polled, before sending a new WRITE instruction. The Write-In-Process (WIP) bit is read-only, and indicates whether the memory is busy with a Write operation. A '1' indicates that a write is in progress, and a '0' that no write is in progress. The Write Enable Latch (WEL) bit indicates the status of the write enable latch. It, too, is read-only. Its value can only be changed by one of the events listed in the previous paragraph, or as a result of executing WREN or WRDI instruction. It cannot be changed using a WRSR instruction. A '1' indicates that the latch is set (the forthcoming Write instruction will be executed), and a '0' that it is reset (and any forthcoming Write instructions will be ignored). The Block Protect (BP0 and BP1) bits indicate the amount of the memory that is to be writeprotected. These two bits are non-volatile. They are set using a WRSR instruction.
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M95040, M95020, M95010
Figure 5. RDSR: Read Status Register Sequence
S 0 C INSTRUCTION D STATUS REG. OUT HIGH IMPEDANCE Q 7 MSB
AI01444
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
6
5
4
3
2
1
0
Figure 6. Block Diagram
HOLD W S C D Q Control Logic
High Voltage Generator
I/O Shift Register
Address Register and Counter
Data Register Status Register
Size of the Read only EEPROM area
Y Decoder
16 Bytes
X Decoder
AI01272B
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M95040, M95020, M95010
Table 5. Write Protected Block Size
Status Register Bits Protected Block BP1 0 0 1 1 BP0 0 1 0 1 none Upper quarter Upper half Whole memory M95040 none 180h - 1FFh 100h - 1FFh 000h - 1FFh M95020 none C0h - FFh 80h - FFh 00h - FFh M95010 none 060h - 7Fh 040h - 7Fh 000h - 7Fh Array Addresses Protected
During a Write operation (whether it be to the memory area or to the status register), all bits of the status register remain valid, and can be read using the RDSR instruction. However, during a Write operation, the values of the non-volatile bits (BP0, BP1) become frozen at a constant value. The updated value of these bits becomes available when a new RDSR instruction is executed, after completion of the write cycle. On the other hand, the two read-only bits (WEL, WIP) are dynamically updated during internal write cycles. Using this facility, it is possible to poll the WIP bit to detect the end of the internal write cycle. Write Status Register (WRSR) The format of the WRSR instruction is shown in Figure 7. After the instruction and the eight bits of the status register have been latched-in, the internal Write cycle is triggered by the rising edge of the S line. This must occur after the falling edge of the 16th clock pulse, and before the rising edge of the 17th clock (as indicated in Figure 7), otherwise the internal write sequence is not performed. The WRSR instruction is used to select the size of memory area that is to be write-protected.
The BP1 and BP0 bits of the status register have the appropriate value (see Table 5) written into them after the contents of the protected area of the EEPROM have been written. The initial delivery state of the BP1 and BP0 bits is 00, indicating a write-protection size of 0. Read Operation The chip is first selected by holding S low. The serial one byte read instruction is followed by a one byte address (A7-A0), each bit being latchedin during the rising edge of the clock (C). The most significant bit, A8, of the address is incorporated as bit b3 of the instruction byte, as shown in Table 3. The data stored in the memory, at the selected address, is shifted out on the Q output pin. Each bit is shifted out during the falling edge of the clock (C) as shown in Figure 8. The internal address counter is automatically incremented to the next higher address after each byte of data has been shifted out. The data stored in the memory, at the next address, can be read by successive clock pulses. When the highest address is reached, the address counter rolls over to "0000h", allowing the read cycle to be continued indefinitely. The read operation is terminated by deselecting the chip.
Figure 7. WRSR: Write Status Register Sequence
S 0 C INSTRUCTION STATUS REG. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D HIGH IMPEDANCE Q
AI01445
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M95040, M95020, M95010
Figure 8. Read EEPROM Array Operation Sequence
S 0 C INSTRUCTION BYTE ADDRESS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
D
A8
A7 A6 A5 A4 A3 A2 A1 A0 DATA OUT 7 6 5 4 3 2 1 0
AI01440
HIGH IMPEDANCE Q
Note: 1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don't Care.
Table 6. Address Range Bits
Device Address Bits M95040 A8-A0 M95020 A7-A0 M95010 A6-A0
The chip can be deselected at any time during data output. If a read instruction is received during a write cycle, it is rejected, and the memory device deselects itself. Byte Write Operation Before any write can take place, the WEL bit must be set, using the WREN instruction. The write state is entered by selecting the chip, issuing three bytes of instruction and address, and one byte of data. Chip Select (S) must remain low throughout the operation, as shown in Figure 10. The product must be deselected just after the eighth bit of the data byte has been latched in, as shown in Figure 10, otherwise the write process is cancelled. As Figure 9. Write Enable Latch Sequence
S 0 C 1 2 3
soon as the memory device is deselected, the selftimed internal write cycle is initiated. While the write is in progress, the status register may be read to check the status of the BP1, BP0, WEL and WIP bits. In particular, WIP contains a `1' during the self-timed write cycle, and a `0' when the cycle is complete, (at which point the write enable latch is also reset). Page Write Operation A maximum of 16 bytes of data can be written during one Write time, tW, provided that they are all to the same page (see Figure 6). The Page Write operation is the same as the Byte Write operation, except that instead of deselecting the device after the first byte of data, up to 31 additional bytes can be shifted in (and then the device is deselected after the last byte). Any address of the memory can be chosen as the first address to be written. If the address counter reaches the end of the page (an address of the
4
5
6
7
D HIGH IMPEDANCE Q
AI01441
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M95040, M95020, M95010
Figure 10. Byte Write Operation Sequence
S 0 C INSTRUCTION BYTE ADDRESS DATA BYTE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
D
A8
A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
HIGH IMPEDANCE Q
AI01442
Note: 1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don't Care.
Figure 11. Page Write Operation Sequence
S 0 C INSTRUCTION BYTE ADDRESS DATA BYTE 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
D
A8
A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
7
S 10+8N 11+8N 12+8N 13+8N 14+8N 15+8N 8+8N 9+8N
136
137
138
139
140
141 2
142 1
24 25 26 27 28 29 30 31 C DATA BYTE 2
DATA BYTE N
DATA BYTE 16
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
0
AI01443
Note: 1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don't Care.
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M95040, M95020, M95010
form xxxx 1111) and the clock continues, the counter rolls over to the first address of the same page (xxxx 0000) and over-writes any previously written data. As before, the Write cycle only starts if the S transition occurs just after the eighth bit of the last data byte has been received, as shown in Figure 11. DATA PROTECTION AND PROTOCOL SAFETY To protect the data in the memory from inadvertent corruption, the memory device only responds to correctly formulated commands. The main security measures can be summarized as follows: - The WEL bit is reset at power-up. - S must rise after the eighth clock count (or multiple thereof) in order to start a non-volatile write cycle (in the memory array or in the status register). - Accesses to the memory array are ignored during the non-volatile programming cycle, and the programming cycle continues unaffected. - After execution of a WREN, WRDI, or RDSR instruction, the chip enters a wait state, and waits to be deselected. - Invalid S and HOLD transitions are ignored. POWER ON STATE After power-on, the memory device is in the following state: - low power stand-by state - deselected (after power-on, a high-to-low transition is required on the S input before any operations can be started). - not in the hold condition - the WEL bit is reset - the BP1 and BP0 bits of the status register are unchanged from the previous power-down (they are non-volatile bits). INITIAL DELIVERY STATE The device is delivered with the memory array in a fully erased state (all data set at all 1s or FFh). The status register bits are initialized to 00h, as shown in Table 7. Table 7. Initial Status Register Format
b7 1 1 1 1 0 0 0 b0 0
Table 8. Input Parameters1 (TA = 25 C, f = 5 MHz)
Symbol COUT CIN Parameter Output Capacitance (Q) Input Capacitance (D) Input Capacitance (other pins)
Note: 1. Sampled only, not 100% tested.
Test Condition
Min.
Max. 8 8 6
Unit pF pF pF
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M95040, M95020, M95010
Table 9. DC Characteristics (TA = -40 to 85 C or -40 to 125 C; VCC = 4.5 to 5.5 V) (TA = -40 to 85 C; VCC = 2.5 to 5.5 V) (TA = -20 to 85 C; VCC = 1.8 to 3.6 V)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Voltage Range all all 4.5-5.5 4.5-5.5 ICC Supply Current 2.5-5.5 1.8-3.6 4.5-5.5 ICC1 Supply Current (Stand-by) 4.5-5.5 2.5-5.5 1.8-3.6 VIL VIH Input Low Voltage Input High Voltage all all 4.5-5.5 VOL1 Output Low Voltage 4.5-5.5 2.5-5.5 1.8-3.6 4.5-5.5 VOH1 Output High Voltage 4.5-5.5 2.5-5.5 1.8-3.6 6 5 6 3 6 5 all all 6 3 6 5 6 3 6 5 IOL = 2 mA, VCC = 5 V IOL = 2 mA, VCC = 5 V IOL = 1.5 mA, VCC = 2.5 V IOL = 0.15 mA, VCC = 1.8 V IOH = -2 mA, VCC = 5 V IOH = -2 mA, VCC = 5 V IOH = -0.4 mA, VCC = 2.5 V IOH = -0.1 mA, VCC = 1.8 V 0.8 VCC 0.8 VCC 0.8 VCC 0.8 VCC Temp. Range all all 6 3 C = 0.1 VCC/0.9. VCC at 5 MHz, VCC = 5 V, Q = open C = 0.1 VCC/0.9. VCC at 2 MHz, VCC = 5 V, Q = open C = 0.1 VCC/0.9. VCC at 2 MHz, VCC = 2.5 V, Q = open C = 0.1 V CC/0.9. VCC at 1 MHz, VCC = 1.8 V, Q = open S = VCC, VIN = VSS or VCC , VCC = 5 V S = VCC, VIN = VSS or VCC , VCC = 5 V S = VCC, VIN = VSS or VCC , VCC = 2.5 V S = VCC, VIN = VSS or VCC , VCC = 1.8 V - 0.3 0.7 VCC Test Condition Min. Max. 2 2 5 5 2 2 10 10 2 2 0.3 VCC VCC+1 0.4 0.4 0.4 0.3 Unit A A mA mA mA mA A A A A V V V V V V V V V V
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
10/18
M95040, M95020, M95010
Table 10A. AC Characteristics
M95040, M95020, M95010 Symbol Alt. Parameter VCC=4.5 to 5.5 V VCC=4.5 to 5.5 V TA=-40 to 85C TA=-40 to 125C Min fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH 1 tCL 1 tCLCH 2 tCHCL 2 tDVCH tCHDX tDLDH 2 tDHDL 2 tHHCH tHLCH tCLHL tCLHH tSHQZ 2 tCLQV tCLQX tQLQH 2 tQHQL 2 tHHQX 2 tHLQZ 2 tW tDIS tV tHO tRO tFO tLZ tHZ tWC tCLH tCLL tRC tFC tDSU tDH tRI tFI tCD fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Data In Rise Time Data In Fall Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock Low Set-up Time before HOLD Active Clock Low Set-up Time before HOLD not Active Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Low-Z HOLD Low to Output High-Z Write Time 0 50 50 50 100 10 70 40 0 0 100 60 0 100 100 100 250 10 20 30 1 1 140 90 0 0 250 150 D.C. 90 90 100 90 90 90 90 1 1 40 50 1 1 Max 5 Min D.C. 200 200 200 200 200 200 200 1 1 Max 2 MHz ns ns ns ns ns ns ns s s ns ns s s ns ns ns ns ns ns ns ns ns ns ns ms Unit
Note: 1. tCH + tCL 1 / fC. 2. Value guaranteed by characterization, not 100% tested in production.
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M95040, M95020, M95010
Table 10B. AC Characteristics
M950x0-W Symbol Alt. Parameter M950x0-R Unit VCC=2.5 to 5.5 V VCC=1.8 to 3.6 V TA=-40 to 85C TA=-20 to 85C Min fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH 1 tCL 1 tCLCH 2 tCHCL 2 tDVCH tCHDX tDLDH 2 tDHDL 2 tHHCH tHLCH tCLHL tCLHH tSHQZ 2 tCLQV tCLQX tQLQH 2 tQHQL 2 tHHQX 2 tHLQZ 2 tW tDIS tV tHO tRO tFO tLZ tHZ tWC tCLH tCLL tRC tFC tDSU tDH tRI tFI tCD fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Data In Rise Time Data In Fall Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock Low Set-up Time before HOLD Active Clock Low Set-up Time before HOLD not Active Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Low-Z HOLD Low to Output High-Z Write Time 0 100 100 100 250 10 140 90 0 0 250 150 0 200 200 250 500 10 40 50 1 1 350 200 0 0 500 380 D.C. 200 200 200 200 200 200 200 1 1 60 100 1 1 Max 2 Min D.C. 400 400 300 400 400 400 400 1 1 Max 1 MHz ns ns ns ns ns ns ns s s ns ns s s ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. tCH + tCL 1 / fC. 2. Value guaranteed by characterization, not 100% tested in production.
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M95040, M95020, M95010
Table 11. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages Output Load 50 ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC CL = 100 pF
0.8VCC 0.7VCC 0.3VCC
AI00825
Figure 12. AC Testing Input Output Waveforms
0.2VCC
Note: 1. Output Hi-Z is defined as the point where data is no longer driven.
Figure 13. Serial Input Timing
tSHSL S tCHSL C tDVCH tCHDX D MSB IN tDLDH tDHDL tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
HIGH IMPEDANCE
AI01447
Figure 14. Hold Timing
S tHLCH tCLHL C tCLHH tHLQZ Q tHHQX tHHCH
D
HOLD
AI01448
13/18
M95040, M95020, M95010
Figure 15. Output Timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D
ADDR.LSB IN
tCL
tSHQZ
LSB OUT
AI01449B
ORDERING INFORMATION The notation used for the device number is as shown in Table 12. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
Table 12. Ordering Information Scheme
Example: M95040 -W MN 6 TR
Memory Capacity3 040 020 010 4 Kbit (512 x 8) with positive clock strobe 2 Kbit (256 x 8) with positive clock strobe 1 Kbit (128 x 8) with positive clock strobe 5 6 3
1
Option TR Tape and Reel Packing
Temperature Range -20 C to 85 C -40 C to 85 C -40 C to 125 C
Operating Voltage blank 4.5 V to 5.5 V W R2 2.5 V to 5.5 V 1.8 V to 3.6 V BN MN DW
Package PSDIP8 (0.25 mm frame) SO8 (150 mil width) TSSOP8 (169 mil width)
Note: 1. Temperature range available only on request, in V CC range 4.5 V to 5.5 V only. 2. The -R version (VCC range 1.8 V to 3.6 V) only available in temperature range 5. 3. All devices use a positive clock strobe: Data In is strobed on the rising edge of the clock (C) and Data Out is synchronized from the falling edge of the clock.
14/18
M95040, M95020, M95010
Table 13. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm Symb. Typ. A A1 A2 B B1 C D E E1 e1 eA eB L N 3.00 8 2.54 7.62 Min. 3.90 0.49 3.30 0.36 1.15 0.20 9.20 - 6.00 - 7.80 Max. 5.90 - 5.30 0.56 1.65 0.36 9.90 - 6.70 - - 10.00 3.80 0.118 8 0.100 0.300 Typ. Min. 0.154 0.019 0.130 0.014 0.045 0.008 0.362 - 0.236 - 0.307 Max. 0.232 - 0.209 0.022 0.065 0.014 0.390 - 0.264 - - 0.394 0.150 inches
Figure 16. PSDIP8 (BN)
A2 A1 B B1 D
N
A L eA eB C
e1
E1
1
E
PSDIP-a
Note: 1. Drawing is not to scale.
15/18
M95040, M95020, M95010
Table 14. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm Symb. Typ. A A1 B C D E e H h L N CP 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
Figure 17. SO8 narrow (MN)
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Note: 1. Drawing is not to scale.
16/18
M95040, M95020, M95010
Table 15. TSSOP8 - 8 lead Thin Shrink Small Outline
mm Symb. Typ. A A1 A2 B C D E E1 e L N CP 0.65 0.05 0.85 0.19 0.09 2.90 6.25 4.30 - 0.50 0 8 0.08 Min. Max. 1.10 0.15 0.95 0.30 0.20 3.10 6.50 4.50 - 0.70 8 0.026 0.002 0.033 0.007 0.004 0.114 0.246 0.169 - 0.020 0 8 0.003 Typ. Min. Max. 0.043 0.006 0.037 0.012 0.008 0.122 0.256 0.177 - 0.028 8 inches
Figure 18. TSSOP8 (DW)
D
N
DIE
C
E1 E
1
N/2
A1
A A2
L
CP
B
e TSSOP
Note: 1. Drawing is not to scale.
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M95040, M95020, M95010
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